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From: cprice@mips.COM (Charlie Price)
Newsgroups: comp.arch
Subject: Re: MIPS R[236]000 interrupts (was Workstation Data Integrity)
Message-ID: <41105@mips.mips.COM>
Date: 26 Aug 90 22:33:24 GMT
References: <1990Aug3.204358.330@portia.Stanford.EDU> <40694@mips.mips.COM> <1990Aug25.014235.6894@mozart.amd.com> <26200@mimsy.umd.edu>
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Reply-To: cprice@mips.COM (Charlie Price)
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In article <26200@mimsy.umd.edu> chris@mimsy.umd.edu (Chris Torek) writes:
>>In article <41066@mips.mips.COM> cprice@mips.COM (Charlie Price) writes:
>>>If an exception occurs during execution of the instruction in a branch
>>>delay slot or "between" a branch and the instruction in the branch-
>>>delay slot, the Cause register has the Branch Delay (BD) bit set and the
>>>EPC register contains the address of the branch instruction.
>
>[and the interrupt handling routine has to emulate the branch]
>
>In article <1990Aug25.014235.6894@mozart.amd.com> tim@proton.amd.com
>(Tim Olson) writes:
>>Just curious -- what happens in the perverse case that someone tries a
>>conditional branch-and-link instruction using the link register as a
>>conditional source ...
>
>There are a number of things you *can* do which are effectively labelled
>`unpredictable'; this is one of them.  If you try it your code misbehaves.
>(The machine continues to function normally, but your program mysteriously
>bombs sometimes.)
>
>(Surely the 29000 has some places where the architecture book says `if
>you do this, you lose'?)

From the "Kane book" description of BGEZAL (one such instruction):

	General register "rs" may not be general register 31,
	because such an instruction is not restartable.
	An attempt to execute this instruction is *not* (italics)
	trapped, however.

This is one of the things that you can trip over with
"simple" pipelined machines,
and I suppose this one isn't all that obvious.
Clearly the assembler should warn you about this dubious usage
similar to the warnings it issues when you write in .noreorder
mode and use a target register in a branch delay slot.
The question is whether it does.
The answer is no, it doesn't.  I've entered a bug report.  Thanks.
-- 
Charlie Price    cprice@mips.mips.com        (408) 720-1700
MIPS Computer Systems / 928 Arques Ave. / Sunnyvale, CA   94086-23650