Path: utzoo!dciem!array!colin
From: colin@array.UUCP (Colin Plumb)
Newsgroups: comp.arch
Subject: Re: Killer Micro II
Message-ID: <603@array.UUCP>
Date: 27 Aug 90 21:09:07 GMT
References: <527@llnl.LLNL.GOV>
Organization: Array Systems Computing, Inc., Toronto, Ontario, CANADA
Lines: 11

Maybe it's a new chip, but BIT announced 100 MFLOPS chips early
this year.  I heard about separate FP add and multiply units, with 192
bits (128 read, 64 write, from their point of view) of 100 MHz bus
each.  2 cycle (20 ns) latency, so they do 50 MFLOPS flow-through.

Now if you can just supply the 2.4 GBytes/second of data these babies
need...  It's still not going to be cheap.  Or easy to cool (28 watts
out of one chip I can almost read by).  But it's going to kill multi-board
ALUs.
-- 
	-Colin