Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!uakari.primate.wisc.edu!caen!acc!jal From: jal@acc (John Lauro) Newsgroups: comp.os.msdos.programmer Subject: Re: Detecting an 80486 Message-ID: <1990Aug27.222630.26146@caen.engin.umich.edu> Date: 27 Aug 90 22:26:30 GMT References: <4562NU013809@NDSUVM1> Sender: news@caen.engin.umich.edu (CAEN Netnews) Organization: University of Michigan - Flint Lines: 24 In article <4562NU013809@NDSUVM1> NU013809@NDSUVM1.BITNET (Greg Wettstein) writes: >It is too bad that the original 8086(8) designers did not have omnipotent >foresight and forsee how well CMOS would scale into the future. If they >would the following instruction would have been set in microcode: > > LMTW AX > >For those of us not omnipotent this translates to Load Machine Type Word. >Where AX receives: (0 = 8086, 1 = 8088, 2 = 80186, 3 = 80286, 4 = 80386) Better yet, AH as cpu, and AL as version of CPU. > >The only concern then is what happens when the number of processors >released exceeds the range of an unsigned 16 bit integer. ;-) > The 386 and I assume 486 do something like that, but only at power up. Check your manuals on conditions after reset. Too bad all 386/486 BIOS makers don't stuff that information somewhere.... An instruction like LMTW would be much better. - John Lauro University of Michigan - Flint