Path: utzoo!attcan!uunet!decwrl!ucbvax!SPICE.CS.CMU.EDU!Alessandro.Forin
From: Alessandro.Forin@SPICE.CS.CMU.EDU
Newsgroups: comp.protocols.tcp-ip
Subject: Re: chip bug or bad dream ? (dream)
Message-ID: <651166097.af@SPICE.CS.CMU.EDU>
Date: 20 Aug 90 15:28:00 GMT
Sender: daemon@ucbvax.BERKELEY.EDU
Organization: The Internet
Lines: 10

The AMD people sent me a mail that cleared up the air: there is a
little note in the spec of the effects of the STOP bit that 
states explicitly "CSR1, CSR2 and CSR3 must be reloaded when the STOP
bit is set".  Needless to say, I had not noticed [lesson: always read 
on to the next page!!].

Apologies to AMD for the rumoring, and BTW I am finding them most
responsive and cooperative.  Thanks!

sandro-