Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!cs.utexas.edu!sdd.hp.com!elroy.jpl.nasa.gov!jarthur!nntp-server.caltech.edu!tybalt.caltech.edu!toddpw From: toddpw@tybalt.caltech.edu (Todd P. Whitesel) Newsgroups: comp.sys.apple2 Subject: Re: DMA detection Message-ID: <1990Aug24.192715.7036@laguna.ccsf.caltech.edu> Date: 24 Aug 90 19:27:15 GMT References: <1990Aug23.224445.3691@utstat.uucp> <1990Aug24.003638.9617@laguna.ccsf.caltech.edu> <1990Aug24.011911.10594@laguna.ccsf.caltech.edu> <1990Aug24.070958.20166@utstat.uucp> Sender: news@laguna.ccsf.caltech.edu Distribution: na Organization: California Institute of Technology Lines: 16 Sorry, I sounded like I was implying that the first four rows of the card are automatically DMA compatible. They aren't, because of the way >4 row cards have to be designed. If the GS RAM+ is supposed to be DMA compatible, then check the TWGS. It is also supposed to require a certain revision level to be DMA campatible. The Zip Chip GS, however, it supposed to be DMA compatible already. According to Zip's representative on America Online, the last custom chip is due back from the factory on monday, and if a week of hard beta-testing works out then they will be going into production. Todd Whitesel toddpw @ tybalt.caltech.edu P.S. Any word on the 20 mhz 65816?