Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!usc!apple!portal!cup.portal.com!mmm
From: mmm@cup.portal.com (Mark Robert Thorson)
Newsgroups: comp.arch
Subject: Re: Killer Micro II
Message-ID: <33387@cup.portal.com>
Date: 30 Aug 90 04:35:58 GMT
References: <527@llnl.LLNL.GOV>
Organization: The Portal System (TM)
Lines: 15

[This is a reposting of comments which do not seem have have made it off
my machine.  My apologies if you see them twice.]

Note that to maintain the
200 MFLOPS rate, you must be doing one ALU and one multiplier result
per clock cycle (each unit is rated at 100 MFLOPS individually), and you
must feed one of the results back to the inputs, because there is only
one output port allowing only one result to be unloaded per clock cycle.
10 ns cycle time in pipelined mode, 2-stage pipeline;  20 ns in flow-thru.
 
It certainly is a powerful chip.  28.6 watts is a lot of power.
 
Other interesting facts:  it comes in a 395-pin PGA.  It costs
$1395 in 100-unit quantity.  A shoebox full of these things would
be worth about a million dollars!