Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uwm.edu!ux1.cso.uiuc.edu!ux1.cso.uiuc.edu!aglew From: aglew@dwarfs.crhc.uiuc.edu (Andy Glew) Newsgroups: comp.arch Subject: Re: What *should* architectural pointers point at? Message-ID: Date: 30 Aug 90 18:03:37 GMT References: <0887@sheol.UUCP> <41167@mips.mips.COM> Sender: usenet@ux1.cso.uiuc.edu (News) Organization: University of Illinois, Computer Systems Group Lines: 27 In-Reply-To: daveg@near.cs.caltech.edu's message of 30 Aug 90 05:51:27 GMT At the cost of an extra bit, and decoding logic, you can encode aligned data field size in the address as follows: abcdefghijkl0 => 1-bit address abcdefghijkl abcdefghijk01 => 2-bit address abcdefghijk0 to abcdefghijk1 abcdefghij011 => 4-bit address abcdefghij00 to abcdefghij11 abcdefghi0111 => 8-bit address abcdefghi000 to abcdefghi111 abcdefgh01111 => 16-bit address abcdefgh0000 to abcdefgh1111 abcdefg011111 => 32-bit address abcdefg00000 to abcdefg11111 abcdef0111111 => 64-bit address abcdef000000 to abcdef111111 abcde01111111 => 128-bit address abcde0000000 to abcde1111111 ... You could, for example, use such an encoding in the literal index or offset field of your instruction. You lose the ability, eg., to take an odd address and add an odd offset to it, in an indexed addressing mode, to get a properly aligned even address, but that's not too much of a loss. Gould used this approach in the PN and NP computers. The same approach can be used on a bus to get sub-field selection. However, byte lane select flags cost only 7 bits (upto 128 bits), and let you handle data that is misaligned wrt bus boundaries in fewer operations. (Eg. MIPS' load-left and load-right conceivably could be done across a bus in this way). -- Andy Glew, a-glew@uiuc.edu [get ph nameserver from uxc.cso.uiuc.edu:net/qi]