Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!usc!snorkelwacker!apple!olivea!orc!inews!mipos2!jsweedle From: jsweedle@mipos2.intel.com (Jonathan Sweedler) Newsgroups: comp.arch Subject: Re: Killer Micro II Message-ID: <2868@inews.intel.com> Date: 30 Aug 90 20:54:53 GMT References: <527@llnl.LLNL.GOV> <603@array.UUCP> <2482@l.cc.purdue.edu> Sender: news@inews.intel.com Reply-To: jsweedle@mipos2.UUCP (Jonathan Sweedler) Organization: Microprocessor Component Group, Intel Corp., Santa Clara, CA Lines: 33 In article mccalpin@perelandra.cms.udel.edu (John D. McCalpin) writes: >More seriously, I keep on hearing rumours from IBM that they want to >know if us users want 128-bit floating-point support on the RISC >system/6000 machines. Apparently the combined adder/multiplier makes >128-bit add/subtract/multiply operations only about 4 times as costly >as 64-bit operations. This is probably coming from Prof. Kahan via IBM. From personal talks with Prof. Kahan and from some postings to the numeric interests mailing list, it seems that Prof. Kahan's next crusade is to convince people that IEEE double precision won't be good enough for future software. He feels that problems tend to grow as systems tend to grow (more memory and become faster). As problems grow, more accuracy is needed. As David Hough wrote, in a letter to the numerics interest group, more precision is needed to: permit grossly unstable algorithms, that parallelize well, to work adequately most of the time, by pushing the roundoff level so far down that it doesn't have enough time to cause trouble for the size of problems likely in the next few years. Both the x86 line and the 68000 line support extended precision. Prof. Kahan thinks this will be ok for the short term, but he feels that in the end, more precision will be needed. It would be interesting to know if other companies are considering support for precisions greater than IEEE double precision. It is interesting to note that at this point, the RISC machines are in a worse position than the CISC machines in this regard. But I probably shouldn't have said this, as I have no desire to start a new RISC vs. CISC war. =============================================================================== Jonathan Sweedler, Microprocessor Design, Intel Corp. UUCP: {decwrl,hplabs,oliveb}!intelca!mipos3!mipos2!jsweedle ARPA: jsweedle%mipos2.intel.com@relay.cs.net