Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!cs.utexas.edu!samsung!munnari.oz.au!goanna!ok From: ok@goanna.cs.rmit.oz.au (Richard A. O'Keefe) Newsgroups: comp.arch Subject: Re: 68040 where is it? Message-ID: <3643@goanna.cs.rmit.oz.au> Date: 31 Aug 90 00:56:52 GMT References: Organization: Comp Sci, RMIT, Melbourne, Australia Lines: 26 In article , pcg@cs.aber.ac.uk (Piercarlo Grandi) writes: > RISCy CISC You got simple instructions and address modes > implemented as they were RISC; complex instructions > and addressing modes are there for backwards > compatibility. > Code is small, CPU has large transistor count, there > are both slow and fast instructions. The CLIPPER tries to find a balance by having a RISC core + "macros". There are nearly 70 of these macros, covering save/restore general registers, conversions, and string instructions. Think of them as common subroutines that are always "in cache" and have a specially cheap calling protocol. (Actually, that reminds me a _lot_ of the DEC-10, with its UUOs.) If I remember correctly, the 29000 does something similar, except that the CLIPPER requires the arguments of its macros to be in specific registers, while the 29000 has three registers "your Nth operand, Mr Macro, comes from this user register". This isn't RISCy CISC; it's CISCy RISC. The CPU is basically RISC+ROM. Same benefits as RISCy CISC except for backwards compatibility. -- You can lie with statistics ... but not to a statistician.