Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!uwm.edu!wuarchive!zaphod.mps.ohio-state.edu!mips!decwrl!shelby!portia.stanford.edu!dhinds From: dhinds@portia.Stanford.EDU (David Hinds) Newsgroups: comp.arch Subject: Re: 64 bits--why stop there? Message-ID: <1990Sep2.015030.4135@portia.Stanford.EDU> Date: 2 Sep 90 01:50:30 GMT References: <1990Aug31.174957.9612@cimage.com> <1990Sep1.062535.7541@rice.edu> Organization: AIR, Stanford University Lines: 18 In article <1990Sep1.062535.7541@rice.edu> preston@titan.rice.edu (Preston Briggs) writes: >Bits are sort of useful as flags and such. >However, I usually want to manage my bit-vectors in large chunks >(getting that 32-way parallelism when ANDing and ORing integers). >But what will we do with pairs and nybbles? >And will we have 1, 2, 4, 8, 16, 32, and 64 bit registers? >We could perhaps manage them like the common idea of using register >pairs for holding double-precision floats. Isn't it obvious how you would manage registers? The register store would also be bit-addressable. So, a 64x64-bit block of registers would be just like a 4096-bit block of memory, and an instruction specifying a register would just need to give a 12-bit short address and a size field. You might require that the alignment of any pseudo-register be at least its own size, but you wouldn't have to. -David Hinds dhinds@popserver.stanford.edu