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From: cik@l.cc.purdue.edu (Herman Rubin)
Newsgroups: comp.arch
Subject: Re: 64 bits--why stop there?
Message-ID: <2505@l.cc.purdue.edu>
Date: 2 Sep 90 12:43:40 GMT
References: <1990Aug31.174957.9612@cimage.com> <1990Sep2.015030.4135@portia.Stanford.EDU>
Organization: Purdue University Statistics Department
Lines: 27

In article <1990Sep2.015030.4135@portia.Stanford.EDU>, dhinds@portia.Stanford.EDU (David Hinds) writes:
> In article <1990Sep1.062535.7541@rice.edu> preston@titan.rice.edu (Preston Briggs) writes:
| >Bits are sort of useful as flags and such.
| >However, I usually want to manage my bit-vectors in large chunks
| >(getting that 32-way parallelism when ANDing and ORing integers).
| >But what will we do with pairs and nybbles?
| >And will we have 1, 2, 4, 8, 16, 32, and 64 bit registers?
| >We could perhaps manage them like the common idea of using register
| >pairs for holding double-precision floats.
> 
>    Isn't it obvious how you would manage registers?  The register store
> would also be bit-addressable.  So, a 64x64-bit block of registers would
> be just like a 4096-bit block of memory, and an instruction specifying
> a register would just need to give a 12-bit short address and a size field.
> You might require that the alignment of any pseudo-register be at least
> its own size, but you wouldn't have to.

Registers should be addressable both as registers, and as memory.  When
addressing the registers as memory, the above operations would be easily
available.  Also, registers could be indexed, etc. (the Univac 1108/1110
and some others had this), which I am sure others besides me would have
liked to have available.  Why not be able to use a short vector in
registers for looping purposes?
-- 
Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907
Phone: (317)494-6054
hrubin@l.cc.purdue.edu (Internet, bitnet)	{purdue,pur-ee}!l.cc!cik(UUCP)