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From: ok@goanna.cs.rmit.oz.au (Richard A. O'Keefe)
Newsgroups: comp.arch
Subject: CLIPPER bit test
Keywords: CLIPPER how-to bits
Message-ID: <3679@goanna.cs.rmit.oz.au>
Date: 4 Sep 90 12:06:17 GMT
Organization: Comp Sci, RMIT, Melbourne, Australia
Lines: 59

I have a question about the Intergraph CLIPPER chip.
Unfortunately, the User's Manual I have dates from when it
was the Fairchild CLIPPER, so my information may be out of date.

The question is "what is the best way to test a few bits in a
register"?  What I'd like to do is
	if bit <A> of <R> is on then
	    if bit <B> of <R> is on then
		on-on action
	    else
		on-off action
	else
	    if bit <B> of <R> is on then
		off-on action
	    else
		off-off action.
where <A>, <B>, and <R> are known at assembly time.  The reason I raise
this question here is that it touches on RISC design.  At the price of
sounding like Herman Rubin, it's something I've often had occasion to do,
in code which was sufficiently critical to warrant hand-coding.

On the VAX and Motorola 88k one has "branch to L if bit B of register R
is set/clear", variously expressed.  On several machines, there is a
"move bit B of register R to the condition codes" instruction (RTPC,
68k, others) or a "set condition codes as if R := R & Mask had been
done, but don't change R".

I can't find anything obvious in the (*old*) CLIPPER manual.  There may
well be a way of doing it in current CLIPPER chips, which would suit me,
but the RISC design question remains.

If there is a spare register T, I can see how to test a bit by doing
	loadq	#Mask, T	; register T := constant Mask
	andw	R, T		; register T &= register R
	brne	L		; goto L if register T not 0
If there aren't any registers spare, we can do it by rotating the bit
in question to the sign bit, then rotating back.  In my case, assuming
that B > A,
	roti	#(31-A),R
	brlt	L_A_on
	roti	#(A-B),R
	brlt	L_A_off_B_on
L_A_off_B_off:
	roti	#(B-31),R
	...
L_A_off_B_on:
	roti	#(B-31),R
L_A_on:
	<obvious>
With this scheme, the cost of the four-way dispatch is 2 conditional
branches (irreducible) and three rotates, and the rotates are supposed
to be single cycle, so I suppose I shouldn't complain too much.

But can testing a bit in a register be so _very_ costly to provide that
it pays to leave it out of a RISC?  Surely it is asking a bit much to
expect a compiler to rediscover tricks like the rotation trick.

-- 
You can lie with statistics ... but not to a statistician.