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From: grege@gold.GVG.TEK.COM (Greg Ebert)
Newsgroups: comp.lsi
Subject: Re: help with large SPICE simulations
Message-ID: <1387@gold.GVG.TEK.COM>
Date: 30 Aug 90 21:51:41 GMT
References: <9008301934.AA11065@fermat.Mayo.edu>
Organization: Grass Valley Group, Grass Valley, CA
Lines: 26

In article <9008301934.AA11065@fermat.Mayo.edu> buchs@MAYO.EDU (Kevin J. Buchs) writes:
>We need to do some large SPICE simulations in terms of devices and
>simulation time.  We really want to do a digital timing simulation of a
>circuit up to the size of a .5K gate array.  Does anyone have experience
>in this and would be willing to lend some pointers?  Note, we are not
>dealing with CMOS but GaAs BJT devices.

My $0.02:

I did a simulation of a large CMOS adder in HSPICE and the execution time
seemed to have an exponential dependency upon circuit size. I broke-down the
circuit to sub-blocks which would be optimized. Starting from the input,
I plotted the output signals, which were loaded by capacitors (CMOS).
After I was satisfied, I used the PWL (piecewise-linear) function to
generate the input to the next stage. After the whole monster was 'optimum',
I ran HSPICE on the whole enchilada, and went home for the weekend. I was
a bit pessimistic with my piece-by-piece approach.

One thing you might want to know is that polysilicon runs don't need
to be modeled as distibuted RC networks, at least in digital simulations.
I used a 'pi' network, with shunt capactitors equal to 1/2 the trace 
capacitance, and a series R equal to the resistance of the entire run. I
also compared to 5 and 7 element networks, and got negligible differences
in overall speed.

As I stated, this was for CMOS, but you might be able to use this for GaAs.