Path: utzoo!utgpu!news-server.csri.toronto.edu!rutgers!usc!snorkelwacker!bloom-beacon!eru!hagbard!sunic!mcsun!unido!mpirbn!p554mve
From: p554mve@mpirbn.mpifr-bonn.mpg.de (Michael van Elst)
Newsgroups: comp.sys.amiga.hardware
Subject: Re: DMA Controllers (was Re:   GVP Trade-in)
Message-ID: <1149@mpirbn.mpifr-bonn.mpg.de>
Date: 31 Aug 90 18:12:39 GMT
References: <1898@lpami.wimsey.bc.ca> <02102.123056@thiger.UUCP> <1990Aug30.195419.25644@sisd.kodak.com>
Reply-To: p554mve@mpirbn.UUCP (Michael van Elst)
Organization: Max-Planck-Institut fuer Radioastronomie, Bonn
Lines: 20

In article <1990Aug30.195419.25644@sisd.kodak.com> jeh@sisd.kodak.com (Ed Hanway) writes:
>My question to all the DMA opponents is this: given that 4 bitplane hires
>overscanned screen DMA does eat up most of the chip memory bandwidth, why
>should processor-controlled I/O be any better than DMA at using the remaining
>bandwidth?  It seems that you would always want to make the most efficient
>use of those precious open bus cycles, and DMA will always be more efficient
>than programmed I/O, although a 68030 tight loop might approach DMA
>efficiency.
Well, even a 68030 needs two cycles for a single word transfer (with
a 32bit bus against a 16bit DMA they would equalize).

The problem with DMA is not in the contention when DMAing to chip memory
but in requesting the bus when the processor (==bus arbiter) waits in
a chip memory cycle.

-- 
Michael van Elst
UUCP:     universe!local-cluster!milky-way!sol!earth!uunet!unido!mpirbn!p554mve
Internet: p554mve@mpirbn.mpifr-bonn.mpg.de
                                "A potential Snark may lurk in every tree."