Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!wuarchive!zaphod.mps.ohio-state.edu!usc!snorkelwacker!bloom-beacon!eru!hagbard!sunic!mcsun!unido!mpirbn!p554mve
From: p554mve@mpirbn.mpifr-bonn.mpg.de (Michael van Elst)
Newsgroups: comp.sys.amiga.hardware
Subject: Re:  GVP Trade-in
Message-ID: <1152@mpirbn.mpifr-bonn.mpg.de>
Date: 1 Sep 90 14:29:10 GMT
References: <589@oregon.oacis.org> <38CP09P@dri.com> <02048.002057@thiger.UUCP> <83242@tut.cis.ohio-state.edu> <1143@mpirbn.mpifr-bonn.mpg.de> <03283.AA03283@babylon.UUCP> <02109.124951@thiger.UUCP>
Reply-To: p554mve@mpirbn.UUCP (Michael van Elst)
Organization: Max-Planck-Institut fuer Radioastronomie, Bonn
Lines: 41

In article <02109.124951@thiger.UUCP> skraw@thiger.UUCP (Stephan von Krawczynski) writes:
>which gvp? do you know what brings me down? i did try to get a
>new gvp-controller. in fact i did only reach a production-date of
>may 1990. and this controller had HEAVY problems with sony-opticals
>(in fact we couldn't get them working though we tried hard).
That might be a software problem (all this MODE_SELECT nuisance).
The Sony-MODs are working very like standard harddrives and didn't
show any problems (not with an Amiga but with our DECstations and SUNs).

>as long as i don't see any controller being faster than ALF3 ...
The speed of the controller hardware does not show up in data transfer
figures used in advertisments, at least if you compare those of
single drive operations on an otherwise unloaded system.
The major performance hits in the "several 100KB/s" range comes
from wrong trackskews or annoying read-ahead schemes and that's
a question of the drives firmware (although a clever driver can
compensate for this).

>see other posting. in fact, we both know that the processor
>cannot run into problems having about half of the DMA-cycles
>(to chipmem) available in the system.
Hu ? Chip memory DMA is a lot different to Zorro-II DMA. With
a controller board in a Zorro slot you have to use the same
bus cycles as the 68000.

>btw, if you dma to fast-mem, is the processor able to access
>it at the same time? (i don't know this, please answer)
Well, of course the bus can be used only for a single operation
at the same time. On the other side you don't need the full
bandwidth for a regular program esp. when using a CPU with a cache.
This leaves many cycles free that can be used for disk DMA. This
isn't enough for maximum load of the SCSI bus but regular disk
transfers won't actually stop the cpu. And DMA takes at least
half the bandwidth used by a processor routine.

Regards,
-- 
Michael van Elst
UUCP:     universe!local-cluster!milky-way!sol!earth!uunet!unido!mpirbn!p554mve
Internet: p554mve@mpirbn.mpifr-bonn.mpg.de
                                "A potential Snark may lurk in every tree."