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From: shepard@finch.pa.dec.com (Mark Shepard)
Newsgroups: comp.sys.m68k
Subject: WANTED: info on DMAcontrollers for 680x0
Message-ID: <1990Sep3.081020.26060@wrl.dec.com>
Date: 3 Sep 90 08:10:20 GMT
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Originator: shepard@finch.pa.dec.com

I'm curious about the tradeoffs involved in implimenting DMA.

Current DMA controller chips, such as intel's 8237 or even the mc68450,
seem ill-suited to use in 32-bit microprocessor systems.  Not only do the
chips interface poorly to the more complex busses (such as the 68030's with
dynamic bus sizing), but the chips may actually be slower than the CPU+cache!

Are designers moving away from standard DMA chips, and instead designing
custom DMA logic into ASICs for each system?  Can anyone describe the
DMA architecture of pc systems such as the Mac (or MacII) and Amiga, and
high-end workstations such as Apollo and HP?

In the specific case of a SCSI controller (a 5380 or DP8490) in a 68030 or
040 system (at 25MHz say), how seriously will NOT using a DMA controller
(ie device which can become a bus master and transfer data quickly) affect
system performance?  It seems that the most serious hit would be in the
context switch (saving/restoring 68030 registers) to service interrupts
required to process each SCSI command.  Even if a DMA controller is used to
transfer SCSI data to/from memory, to perform a single SCSI transaction
(ie reading a specific chuck of data into memory) requires several SCSI 
commands, each of which needs to be serviced by the main cpu.  Can someone
with experience with SCSI comment on how significant this overhead is?

I believe NCR is addressing this last point with "smart" SCSI controllers
which are able to handle entire transactions w/o cpu intervention.  
Can anyone who has used these chips give me a better description?

Finally (just for the record), a Motorola application note suggests
using a dedicated 68020 (plus some buffers and control logic) as
a DMA controller.  Anyone know of a system using this approach?  
It seems like it would be simpler to just use the extra cpu as an io processor.

Thanks for any comments,

Mark Shepard  shepard@{decpa.pa,gatekeeper}.dec.com