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From: henry@ginger.sri.com (Henry Pasternack)
Newsgroups: comp.sys.m68k
Subject: Designing memory for cache-burst access.
Message-ID: <15852@unix.SRI.COM>
Date: 3 Sep 90 21:31:08 GMT
Sender: news@unix.SRI.COM
Reply-To: henry@ginger.sri.com (Henry Pasternack)
Organization: SRI International
Lines: 22


   I'm still looking for some detailed advice on DRAM memory system
design.  Here's another question:

   As I understand it, the 68030 allows cache-burst access from
arbitrary long word addresses.  This means that there is no guarantee 
that a cache burst will begin and end within the same page.  The
implication is that the memory controller must check for page access
and terminate the cache-burst access early if necessary.  This is
something of a nuisance in a nibble-mode memory where the column
address is only available internal to the DRAM.  It's even a nuisance
with fast page-mode DRAM's (but a necessary one).

   Is there someone out there who can describe to me in some detail
the tradeoffs involved in selecting nibble-mode or fast page mode
DRAM's for application with the 68030?  I'm not looking for a beginners
tutorial, but some detailed information on real applications to help 
speed my learning process.

   Thanks a lot.

-Henry