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From: jeremy@sinope.socs.uts.edu.au (Jeremy Fitzhardinge)
Newsgroups: comp.arch
Subject: Re: 64 bits--why stop there?
Message-ID: <18286@ultima.socs.uts.edu.au>
Date: 5 Sep 90 02:47:41 GMT
References: <6106@vanuata.cs.glasgow.ac.uk> <2437@crdos1.crd.ge.COM> <1990Aug31.174957.9612@cimage.com> <3656@goanna.cs.rmit.oz.au> <1990Sep2.220249.19420@cimage.com> <1381@svin02.info.win.tue.nl>
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rcpieter@svin02.info.win.tue.nl (Tiggr) writes:

>>Does anyone seriously believe that a sane computer vendor will create
>>a new flavor of hardware in the nineties, with no evidence of any
>>customers?
>
>Who claims there is no evidence of customers?  And if there are
>customers, somebody will jump in the market with something to suit
>there needs.  I wouldn't mind to have a nice machine with 64bit
>registers, databus and addressbus, where the addressbus adresses
>bits, and not bytes, giving 2^64 BITS of memory.  What I don't
>really like is thinking about alignment restrictions...

There already processors in use that have full bit addressing - the
TI340x0 GSP (graphics system processor) series. All pointers are bit
aligned, and all memory operations are 1 to 32 bits wide. The exception
to this is that instructions must be word (16 bit) aligned and performance
drops greatly if the stack isn't aligned. Obviously, since it is 32 bit,
it doesn't have the large, general purpose capability as a 64 bit processor,
but as a co-processor in a system it is really useful. Compression algoithms
such as LZW come out very cleanly, and of course graphics work (supported
in microcode) is very efficent. No doubt there are many algorithms that can
benefit from reading arbitary word widths from arbitary bit offsets.
The assembly language is similar to something like a 680x0, and is thus
quite useable by a compiler, with lots of general purpose registers
(15 that a compiler can safely use, for both addresses and data).

The C compiler I use on it is a subset of C that doesn't take full advantage
of the hardware - it doesn't even support bit fields, let alone an extention
to specify the size of variables. Naturally pointers to objects are to their
bit addresses, and sizeof(char)==1 even although its 8 memory locations wide.

Not surprisingly, the bus interface is a mass of barrel shifters, with a
very complex set of timing calculations. This is because the bus interface
is semi-autonomous with respect to the ALU/processor core, and the nature
of operations that can be performed. The memory interface is 16 bits wide
only, so other sized operations on the memory result in Read-Modify-Write
cycles. The bus controller can also do a range of arithmetic and logical
operations on memory bit fields as support for the graphics instruction
modes.
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Jeremy Fitzhardinge: jeremy@ultima.socs.uts.edu.au  | My hovercraft is full of
No Comment.          jeremy@utscsd.csd.uts.edu.au   | eels.