Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!rutgers!maverick.ksu.ksu.edu!ux1.cso.uiuc.edu!mcs.anl.gov!midway!mimsy!chris From: chris@mimsy.umd.edu (Chris Torek) Newsgroups: comp.arch Subject: Re: Is handling off-alignment important? Message-ID: <26376@mimsy.umd.edu> Date: 5 Sep 90 16:15:58 GMT References: <104037@convex.convex.com> <8840014@hpfcso.HP.COM> <140356@sun.Eng.Sun.COM> Organization: U of Maryland, Dept. of Computer Science, Coll. Pk., MD 20742 Lines: 34 (Someone is recirculating old news through the net. The last time this came around, I did not comment, but this time I cannot resist :-) ) [Someone asks what machines that require alignment do with unaligned addresses in loads. His `least desirable' scenario is that the processor completely ignores the low address bits.] In article <140356@sun.Eng.Sun.COM> jputnam@raptor.Eng.Sun.COM (James M. Putnam) writes: >The VAX does this for quad word loads. VAX LISP takes advantage of >this feature to get two free tag bits on LISP pointers that don't >need to be masked before being dereferenced. Since there is no mention of this in the VAX architecture handbook, I tried it out to make sure. An unaligned movq reads the unaligned quadword. If r0 contains 0x1003 and memory at 0x1000 looks like this: 0x1000: 0x00 0x1001: 0x01 0x1002: 0x02 r0 -> 0x1003: 0x03 0x1004: 0x04 0x1005: 0x05 0x1006: 0x06 0x1007: 0x07 0x1008: 0x08 0x1009: 0x09 0x100a: 0x0a then after a `movq (r0),r0', r0 contains the value 0x06050403 and r1 contains the value 0x0a090807. -- In-Real-Life: Chris Torek, Univ of MD Comp Sci Dept (+1 301 405 2750) Domain: chris@cs.umd.edu Path: uunet!mimsy!chris