Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!ucsd!network.ucsd.edu!celit!dave From: dave@fps.com (Dave Smith) Newsgroups: comp.arch Subject: Re: What *should* architectural pointers point at? Message-ID: <11201@celit.fps.com> Date: 5 Sep 90 01:51:53 GMT References: <0887@sheol.UUCP> <11192@celit.fps.com> <2504@l.cc.purdue.edu> Sender: daemon@fps.com Reply-To: dave@fps.com (Dave Smith) Organization: FPS Computing Inc., San Diego CA Lines: 44 In article <2504@l.cc.purdue.edu> cik@l.cc.purdue.edu (Herman Rubin) writes: >But what if k bits, starting from the n-th bit, are wanted? This is not >all that uncommon, and may be needed frequently, including supercomputers. Shift to the left, shift to the right do some or's. What you're asking for makes the hardware more complex and therefore SLOWER! I'm not a hardware designer but I listen to them whine and moan all the time about these kinds of things, so let me put forth what I think would be needed to do that (y'all can flame me if you like) Ok, here's some ways to give k bits starting at the n-th bit: a) A bit-addressable memory, n (call it 32) bits wide. So, it has a lot of 1 bit wide memory cells. Any one of these bits can be bit 0 thru n on the output bus. How do you hook the memories to the bus? Each cell to each line of the bus? Ick! Lots of circuitry and lots of (overlapping!) traces on your board. A cross-bar circuit would work but those are expensive. We could load the memories into a barrel shifter and then shift and then do another load. b) Do the work on the processor end. This pretty much means you've gotta do shifts since your memory will be giving you word aligned data. No crossbars here. You'll have to do two memory fetches on non-word aligned fetches. c) 1 bit data path. This is silly, but it does supply the wanted functionality. Suppose you go ahead and do the circuitry for this. This means this circuitry is in the critical path for data fetches, ALWAYS. Even when it's not used, it's another layer of circuitry. When you're working with faster machines, nano-seconds count. Most of the time you'll be working with 32-bit word, or even double-word aligned data. So why pay the extra penalty for this circuitry on _every_ data fetch? All you're doing is hiding the bus from the programmer. Let the compiler do that for you (sorry, Herman, I know how you feel about HLL's). Byte addressing is bad enough and a lot of people probably wouldn't support if it weren't for the fact that a lot of I/O devices require you to be able to write only one byte to a certain address and nothing more. Communications protocols that are byte-aligned make processing them go slower and don't even start me off on bit-stuffed formats (thank YOU, ISO for ASN.1!). -- David L. Smith FPS Computing, San Diego ucsd!celerity!dave or dave@fps.com