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From: tif@doorstop.austin.ibm.com (Paul Chamberlain/32767)
Newsgroups: comp.arch
Subject: Re: Workstation Data Integrity
Message-ID: <3405@awdprime.UUCP>
Date: 6 Sep 90 15:54:45 GMT
References: <6797.26d6edce@vax1.tcd.ie> <56qmo1w162w@zl2tnm.gp.govt.nz> <19875@crg5.UUCP> <19208@dime.cs.umass.edu> <2201@lectroid.sw.stratus.com> <68362@sgi.sgi.com> <1990Sep4.163619.24726@zoo.toronto.edu> <68505@sgi.sgi.com> <2483@crdos1.crd.ge.COM>
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Reply-To: tif@doorstop.austin.ibm.com (Paul Chamberlain/32767)
Organization: IBM AWD, Austin, TX
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In article <2483@crdos1.crd.ge.COM> davidsen@crdos1.crd.ge.com (bill davidsen) writes:
>In article <68505@sgi.sgi.com> karsh@trifolium.sgi.com (Bruce Karsh) writes:
>
>| Given that a memory system is otherwise properly designed and tested
>| and uses modern 4Mbit DRAM memory chips, is there any evidence that
>| memory parity makes a measurable difference in the silent wrong answer
>| rate?
>
>  If the error rate for 1 bit error is 1 in N, then the rate for a 2 bit
>error is 1 in N^2. With N in the order of some millions (or billions),
>you make the chance of silent error millions of time less likely.

I do not pretend to answer the original question but only to say that
this answer is unfounded.  According to my statistics class this is only
true if the two events are independent.  Perhaps the question could have
been read as:

	... is there any evidence that there are measurably more single
	bit errors than multiple bit errors?

And now for a slightly biased question:  Is it typical for a workstation
to provide ECC and memory scrubbing like the Risc System/6000 does?  I
am getting at another possible selling point of this machine.

Paul Chamberlain | I do NOT represent IBM         tif@doorstop, sc30661@ausvm6
512/838-7008     | ...!cs.utexas.edu!ibmaus!auschs!doorstop.austin.ibm.com!tif