Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!wuarchive!udel!rochester!crowl From: crowl@cs.rochester.edu (Lawrence Crowl) Newsgroups: comp.arch Subject: Re: What *should* architectural pointers point at? Message-ID: <1990Sep7.010252.19755@cs.rochester.edu> Date: 7 Sep 90 01:02:52 GMT References: <0887@sheol.UUCP> <2491@l.cc.purdue.edu> <26DE7EE3.58FC@tct.uucp> Reply-To: crowl@cs.rochester.edu (Lawrence Crowl) Organization: University of Rochester Computer Science Dept Lines: 15 In article <26DE7EE3.58FC@tct.uucp> chip@tct.uucp (Chip Salzenberg) writes: >We are discussing machines where the *address space* is too large for 32 >bits. For widely-used machines, physical memory will usually be less than >four gigabytes, and thus 32-bit addressable. A bit granularity in virtual addresses does not imply a bit granularity in physical addresses. For instance, we could have a bit-grain 64-bit virtual address and a word-grain 32-bit physical address. Before anyone jumps on me for such a bizzare notion, note that some microprocessors do not provide the low bit (or two) of the physical address on the pinout. (Although some have byte select pins, from which you can infer the address.) -- Lawrence Crowl 716-275-9499 University of Rochester crowl@cs.rochester.edu Computer Science Department ...!{ames,rutgers}!rochester!crowl Rochester, New York, 14627