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From: davec@neutron.amd.com (Dave Christie)
Newsgroups: comp.arch
Subject: Re: Workstation Data Integrity
Message-ID: <1990Sep8.012554.27373@mozart.amd.com>
Date: 8 Sep 90 01:25:54 GMT
References: <19208@dime.cs.umass.edu> <1990Sep6.141040.3244@mozart.amd.com> <2496@crdos1.crd.ge.COM> <1990Sep7.003451.13193@portia.Stanford.EDU> <1990Sep7.144514.19015@mozart.amd.com> <2253@lectroid.sw.stratus.com>
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Reply-To: davec@nucleus.amd.com (Dave Christie)
Organization: Advanced Micro Devices, Inc., Austin, Texas
Lines: 40

In article <2253@lectroid.sw.stratus.com> dswartz@bigbootay.sw.stratus.com (Dan Swartzendruber) writes:
>In article <1990Sep7.144514.19015@mozart.amd.com> I write:
>:
>:	1) it would take almost twice as long to check the parity,
>:	   (7 levels of XOR vs. 4), and parity checking tends to be a
>:	   time critical path (although sometimes you can delay it), 
>:	   so it's a classic realestate/speed tradeoff
>
>Beg pardon?  You're telling me that all of these parity checks are done
>in serial???  If not, what difference does it make how many check bits
>there are?

Parity is typically generated and checked with a tree of 2-bit 
exclusive-ORs.  Generating  (or regenerating) 8-bit parity takes 
3 levels of XOR.  For an 8-byte word, you need three more levels to 
combine these into a single bit.  Comparing the regenerated bit(s) 
with the stored bit(s) on a read requires one more XOR for each bit.  
As for generating an error signal, the 9 levels of XOR do it directly 
for 64-bit parity.  With 8-bit parity on a 64-bit word the eight
error signals you have after 4 levels of XOR must be combined with
(logically) three levels of 2-bit OR, which in any technology will be 
somewhat faster than 3 levels of XOR, and can often be much faster 
(eg. ECL wired logic, CMOS dynamic logic). 

>:
>:	2) byte parity allows byte writes without the control complexity
>:	   of doing read/modify/write.  (EDAC of course requires r/m/w
>:	   for partial-word writes.)
>
>This argument as least doesn't always hold when dealing with a write-back
>cache.

Quite true.  (Providing your I/O system or whatever else you have writing
also does block or word writes, as Bill D. more or less pointed out earlier.)

Just how significant either of these two points are is highly dependent
on many parameters of your memory system design such as cycle time, ram
speed, degree of pipelining, desired latency, write setup time, etc.
------------
Dave Christie