Path: utzoo!utgpu!watserv1!watmath!att!tut.cis.ohio-state.edu!zaphod.mps.ohio-state.edu!wuarchive!uunet!ncrlnk!ncr-mpd!Chuck.Phillips From: Chuck.Phillips@FtCollins.NCR.COM (Chuck.Phillips) Newsgroups: comp.arch Subject: Re: Why floating point hardware: micro-parallelism, micro-cycles Message-ID: Date: 9 Sep 90 20:57:55 GMT References: <197@validgh.com> Sender: uucp@ncr-mpd.FtCollins Followup-To: comp.arch Organization: NCR Microelectronics, Ft. Collins, CO Lines: 50 In-reply-to: dgh@validgh.com's message of 9 Sep 90 15:17:44 GMT >>>>> On 9 Sep 90 15:17:44 GMT, dgh@validgh.com (David G. Hough on validgh) said: David> ...since floating-point instructions can be decomposed into simple David> integer operations, how can they be justified in a RISC David> architecture? Why is it that they don't run as fast in software? David> (They don't, and can't, but you might have to try it to convince David> yourself. All you need to do is look at 64-bit double precision David> floating-point add/subtract on a 32-bit RISC architecture). David> Basically I was attacking the idea that RISC = 'a few simple David> instructions'. This was an overly simple definition anyway. The David> correct definition of RISC architecture is 'good engineering' in the David> sense of 'good engineering economy', although not everybody has David> realized this yet. Perhaps RISC does indeed stand for Reduced Instruction Set, and "good engineering" can, and has, been applied to CISC architectures (notably the 80486 and the 68040). Modern processor design is indeed indebted to the RISC pioneers who, in order to compensate for reduced instruction sets, applied "good engineering" to come up with some remarkable techniques for parallelism. _Except for the reduced number of instructions_, these same techniques can be applied to CISC (albeit some techniques with more difficulty). If a CISC processor _averages_ close to 1 Cycle Per Instruction, what is the advantage of removing many of those instructions? Are you claiming a CISC processor is somehow transformed into a RISC processor because of an improved CPI, _even though the actual instruction set has not diminished_? (e.g. the 68040 & 80486) In a given technology, the physics of the medium limits how fast a switch can toggle, leaving parallelism as the route for even greater throughput. It appears Reduced Instruction Sets and parallelism are, to a great degree, orthagonal. Am I missing something here? Is it possible higher silicon densities will shift (or have shifted) the economics of processor design toward more robust parallelized instruction sets, perhaps even toward "Super CISC"? Just for discussion, David> David Hough David> dgh@validgh.com uunet!validgh!dgh na.hough@na-net.stanford.edu #include -- Chuck Phillips MS440 NCR Microelectronics Chuck.Phillips%FtCollins.NCR.com 2001 Danfield Ct. Ft. Collins, CO. 80525 uunet!ncrlnk!ncr-mpd!bach!chuckp