Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!decwrl!nsc!taux01!amos From: amos@taux01.nsc.com (Amos Shapir) Newsgroups: comp.arch Subject: Re: Why floating point hardware: micro-parallelism, micro-cycles Message-ID: <4565@taux01.nsc.com> Date: 10 Sep 90 15:29:06 GMT References: Organization: National Semiconductor (IC) Ltd, Israel, Home of the Series 32000 Lines: 17 X-Hdate: 20 Elul 5750 [Quoted from the referenced article by Chuck.Phillips@FtCollins.NCR.COM (Chuck.Phillips)] > >In a given technology, the physics of the medium limits how fast a switch >can toggle, leaving parallelism as the route for even greater throughput. >It appears Reduced Instruction Sets and parallelism are, to a great degree, >orthagonal. Am I missing something here? What you're missing is that CISC processors are a bitch to parallelize on the instruction level - each instruction or part thereof can take a different number of cycle and occupy an unpredictable number of resources; when several processors have to share these resources, a lot of effort should be put into interlocking, synchronisation, etc. -- Amos Shapir amos@taux01.nsc.com, amos@nsc.nsc.com National Semiconductor (Israel) P.O.B. 3007, Herzlia 46104, Israel Tel. +972 52 522255 TWX: 33691, fax: +972-52-558322 GEO: 34 48 E / 32 10 N