Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sdd.hp.com!apollo!rehrauer
From: rehrauer@apollo.HP.COM (Steve Rehrauer)
Newsgroups: comp.sys.amiga
Subject: Re: Low cost Macs and The Return of Timex (was Re: Murph's VAPORWARE )
Message-ID: <4caae052.20b6d@apollo.HP.COM>
Date: 7 Sep 90 15:07:00 GMT
References: <9008270223.AA07322@lilac.berkeley.edu> <2788@corpane.UUCP> <4393@grape3.UUCP>
Sender: root@apollo.HP.COM
Reply-To: rehrauer@apollo.HP.COM (Steve Rehrauer)
Organization: Hewlett-Packard Apollo Division - Chelmsford, MA
Lines: 32

In article <4393@grape3.UUCP> king@motcid.UUCP (Steven King) writes:
>In article <2788@corpane.UUCP> sparks@corpane.UUCP (John Sparks) writes:
>>>Another Sinclair.
>>>Sir Clive Sinclair is looking for a partner to develop and
>>>manufacture his design for a 200 MIP bipolar, battery
>
>I'd buy 200 MIPS for this thing.  Don't forget, MIPS (Million Instructions
>Per Second) is not an indication of processor power!  It's an indication of,
>quite literally, the speed at which a processor executes instructions.

It's becoming common for quoted "MIPS" ratings to actually mean performance
on v1.1 of the (brain-dead) dhrystone benchmark, scaled relative to VAX 11/780
performance.  To do this, you compile dhry, run it, take the reported figure,
divide it by the magic number 1757 (what an 11/780 achieved at some point with
some compiler), and voila!  SPECmark figures are obtained much the same way,
relative to 11/780 performance on the (much less brain-dead) SPEC suite.

Using this definition of "MIPS", 200 is VERY respectable.  Who knows what
definition was implied in the Infoworld article.  If it truly was "mega-
instructions per second", then I agree that it's a near-worthless yardstick.

>For the chip Sinclair is talking about, he needs RISC.  I have no doubt he'll
>be able to achieve 200 Million Instructions Per Second.  I also don't doubt
>that it's POSSIBLE for a single processor to emulate any other (yes, even to
>emulate a Cray).  But, if it takes him 200 million instructions to emulate a
>single 68000 instruction I'd say it's not worth the trouble.

Ah, I'd imagine it'd take a bit fewer than 200,000,000, for whatever RISC
architecture he chooses.  If not, he should choose a different one. :-)
--
   >>"Aaiiyeeee!  Death from above!"<<     | (Steve) rehrauer@apollo.hp.com
"Spontaneous human combustion - what luck!"| Apollo Computer (Hewlett-Packard)