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From: hamilton@intersil.uucp
Newsgroups: comp.sys.amiga.hardware
Subject: Re: 2.0 in FRANCES
Message-ID: <153.26e68f95@intersil.uucp>
Date: 6 Sep 90 18:04:05 GMT
References: <444299@neabbs.UUCP>
Organization: Harris Semiconductor, Santa Clara CA
Lines: 65

In article <444299@neabbs.UUCP>, joost@neabbs.UUCP (JOOST BOERHOUT) writes:
> In msg 440507 news.amigahard 28-08-90 Fred Hamilton wrote:
> 
>  FH> The only problem is, FRANCES ram disappears betwen when you reset
>  FH> the computer (control A-A) and when the resident AFM program is executed.
>  FH>
>  FH>  [ ... some stuff deleted ... ]
>  FH>
>  FH> So the only reason that you can have 1.3 in FRANCES ram is because
>  FH> during re-boot the exact same image exists in the WCS/ROMs. So if we ever
>  FH> want to have a chance of using this technique to run 2.0 (without 2.0 in
>  FH> ROM from a Rejuevenator or the like), we'll have to figure out why the
>  FH> 8421 DRAM controller seems to lose its programming and needs to be
>  FH> modeloaded after every reset (*RESET only goes to the REMAPK flip-flop,
>  FH> it doesn't go to the 8421).
> 
> I took a thorough look at the spec of the DP8421 DRAM controller and could
> not find anything which matches the above described behaviour. There is no
> way that the chip 'knows' that a reset cycle is going on.

I _think_ that was my mistake.  I now believe it was locking up because 
when you reset the Amiga it wants to yank KS down to location $000000 and
it probably does other funky stuff that I don't know about during reset.

** If anyone can tell me what an A1000 does during reset I'd appreciate it! **

I'm trying to figure out where the WCS goes, whether or not the "cold boot"
ROMs are ever used again once KickStart is loaded into the WCS, etc.

> So what actually
> happens during a reset of the 68020 ?  The only important thing I can
> imagine is that the address bus will be tri-stated thus writing nonsence
> to the chip !  This could be fixed with a pulldown resistor at A23 or A31.
> I must admit that the above sounds silly but who knows (Murphy :-).

No, the kickstart image remains there, and intact.

> I myself have two problems with FRANCES:
> 
>  1) it needs a warming up of 3 - 5 minutes or so.

Not mine.  Are you using 70-80ns ram?  What clock frequency?  I run at
18MHz with 80ns ram and the minimum wait states (1 or 2, I can't remember).

>  2) AFM alway fails to find FRANCES the first time.

Mine fails about 1 in 3 tries, whether "cold" or "warm".

> I can't explain why FRANCES needs the warming up except the darn thing
> is working on the edge of the (timing) specs. A heated chip will have
> a shift in the timing specs so this seems to be the case.
> I have version 1.11a of the AFM program. This version does not wait for
> the required 60ms initialization time of the DP8421 (I took a gimpse
> of the source). This should explain why AFM always finds FRANCES the
> second time it runs.

Actually the FRANCES board itself waits the 60ms by asserting the *RFIP
output of the 8421 until the initialization is over.  This delays *FDSACK
as long as required (top of the second page of the FRANCES schematics).

> - joost -
-- 
Fred Hamilton                  Any views, comments, or ideas expressed here
Harris Semiconductor           are entirely my own.  Even good ones.
Santa Clara, CA