Path: utzoo!utgpu!watserv1!watmath!att!occrsh!uokmax!apple!usc!samsung!uunet!cbmvax!bryce
From: bryce@cbmvax.commodore.com (Bryce Nesbitt)
Newsgroups: comp.sys.m68k
Subject: Re: Designing memory for cache-burst access.
Message-ID: <14178@cbmvax.commodore.com>
Date: 4 Sep 90 15:10:36 GMT
References: <15852@unix.SRI.COM>
Reply-To: bryce@cbmvax (Bryce Nesbitt)
Organization: Commodore, West Chester, PA
Lines: 26

In article <15852@unix.SRI.COM> henry@ginger.sri.com (Henry Pasternack) writes:
>
>...Here's another question:
>
>   As I understand it, the 68030 allows cache-burst access from
>arbitrary long word addresses.  This means that there is no guarantee 
>that a cache burst will begin and end within the same page.

Not quite.  The 68030 will *start* a cache-burst at an arbitrary address,
then fill in the the remainder of the aligned quad-longword.  You might
see the following:

		$XXXXXX08 -> First  Fetch
		$XXXXXX0C -> Second Fetch
		$XXXXXX00 -> Third  Fetch
		$XXXXXX04 -> Fourth Fetch

The 68030 starts with the longword it actually wanted, then proceeds forward
to the next longword.  After reaching the end it wraps back to backfill
the remainder of the cache line.

-- 
|\_/|  . "ACK!, NAK!, EOT!, SOH!"  "Lawyers: America's untapped export market."
{X o} .     Bryce Nesbitt, Commodore-Amiga, Inc.
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