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From: dwoodwar@undeed.UUCP (Duncan S Woodward)
Newsgroups: comp.sys.transputer
Subject: DISABLING THE PLL ON THE TRANSPUTER
Message-ID: <1123@undeed.UUCP>
Date: 10 Sep 90 16:02:15 GMT
Sender: dwoodwar@Daisy.EE.UND.AC.ZA (Duncan S Woodward)
Reply-To: dwoodwar@undeed.uucp (Duncan R Woodward)
Organization: Univ. Natal, Durban, S. Africa
Lines: 28

HI THERE,

I recently happened to be glancing through INMOS technical note 62 (The
design of a high resolution graphics system using the IMS G300 Colour Video
Controller), and noticed it was possible to disable the clock phase locked
loop (PLL) of the G300 by shorting together the CAP+ and CAP- pins on the
device. The object of doing this was to enable a non standard clock speed (up
to the max for the device) to be supplied via the PLLCLKIN pin to the device.
My question is does this apply to the transputer PLL as well? ie will
shorting CAP+ to CAP- on the transputer disable its PLL? What advantages or
disadvantages would this create (apart from that mentioned for the G300)?
Since the ClockIn and ProcClockOut signals on the transputer appear to have
no specific phase relation, could disabling the PLL and hence making ClockIn
= ProcClockOut; allow one to synchronise processor cycles and external memory
cycles to external hardware driven by ClockIn?

Any comments would be welcome.

Thanks Duncan
      
Duncan Woodward
University of Natal
Durban
South Africa