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Subject: RISC pipelines
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Date: 16 Sep 90 16:21:14 GMT
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Has anyone set up a RISC architecture where you can supply branch
logic as a vector (e.g. an ordered set of ordered pairs along the
lines of substitute "this address" for "that address")?

[I use a variation on this in my own work as a way of implementing
time-critical loops, and I've seen it in some HLL's]