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Subject: Re: RISC pipelines
Message-ID: <11992@chaph.usc.edu>
Date: 16 Sep 90 18:26:27 GMT
References: <11991@chaph.usc.edu>
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In article <11991@chaph.usc.edu> I wrote:
   Has anyone set up a RISC architecture where you can supply branch
   logic as a vector (e.g. an ordered set of ordered pairs along the
   lines of substitute "this address" for "that address")?

um.. the more I think about how I use this, and the more I think about
considerations such as nesting/function calls/restartability, the more
I think no-one would use ordered pairs.  A more appropriate mechanism
(e.g. what I use) is set up the vector, and have an instruction which
fetches the next element and does the branch.

I guess the point I was trying to make is there is a way of removing
branch penalties from deep pipelines.  Presuming you can feed this
information into the prefetch mechanism adequately.

That, and I want to know if any hardware already supports this idea to
any extent.