Path: utzoo!attcan!uunet!ncrlnk!ncr-mpd!Chuck.Phillips
From: Chuck.Phillips@FtCollins.NCR.COM (Chuck.Phillips)
Newsgroups: comp.arch
Subject: Re: Why floating point hardware: micro-parallelism, micro-cycles
Message-ID: <CHUCK.PHILLIPS.90Sep17040818@halley.FtCollins.NCR.COM>
Date: 17 Sep 90 03:08:18 GMT
References: <197@validgh.com>
	<CHUCK.PHILLIPS.90Sep9215755@halley.FtCollins.NCR.COM>
	<41518@mips.mips.COM>
Sender: uucp@ncr-mpd.FtCollins
Organization: NCR Microelectronics, Ft. Collins, CO
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In-reply-to: mash@mips.COM's message of 14 Sep 90 23:41:34 GMT

>>>>> On 14 Sep 90 23:41:34 GMT, mash@mips.COM (John Mashey) said:
John> As noted, good engineering practice is good engineering practice,
John> and it didn't start with RISC.
John> However, the reduced number of instructions is the LEAST of the issues,
John> and people keep getting confused with this.  Much more relevant are
John> issues like:
John> 	Operand and instruction alignment, especially in VM systems
John> 	Number and especially kinds of addressing modes, especially
John> 		multi-level indirect, for example.
John> 	Number & size of operand fetches/writes caused by an instruction
John> 	Multiple instruction sizes
John> 	Number and kind of side-effects caused by an instruction, especially
John> 		in VM systems
John> 	Exception model

Well put.  So how about ditching the RISC acronym for a more descriptive
one?  (e.g. LOUIS - Load/store One Uniform Instruction Size   1/2 :-)

John> -john mashey   DISCLAIMER: <generic disclaimer, I speak for me only, etc>

Ditto.

John> UUCP: 	 mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash 
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John> USPS: 	MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
--
Chuck Phillips  MS440
NCR Microelectronics 			Chuck.Phillips%FtCollins.NCR.com
2001 Danfield Ct.
Ft. Collins, CO.  80525   		uunet!ncrlnk!ncr-mpd!bach!chuckp