Path: utzoo!attcan!uunet!shakti!shri From: shri@ncst.ernet.in (H.Shrikumar) Newsgroups: comp.arch Subject: Re: Why floating point hardware: micro-parallelism, micro-cycles Summary: RISC = REGULAR Instruction set comp ..... Message-ID: <919@shakti.ncst.ernet.in> Date: 17 Sep 90 12:15:43 GMT References: <197@validgh.com> Reply-To: shri@shakti (H.Shrikumar ) Organization: National Centre for Software Technology, Bombay, INDIA Lines: 19 >>>>>> On 9 Sep 90, dgh@validgh.com (David G. Hough on validgh) said: >David> Basically I was attacking the idea that RISC = 'a few simple >David> instructions'. This was an overly simple definition anyway. In article ref. above, (Chuck.Phillips) adds: >Perhaps RISC does indeed stand for Reduced Instruction Set, and "good >engineering" can, and has, been applied to CISC architectures (notably the >80486 and the 68040). If only we defined RISC = REGULAR Instruction Set Computers ..... ^^^^^^^ (and (1/2 :-) CISC = Confusing Instruction Set Computers ? ;-) -- shrikumar ( shri@ncst.in )