Path: utzoo!attcan!uunet!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!mips!winchester!mash
From: mash@mips.COM (John Mashey)
Newsgroups: comp.arch
Subject: Re: Why floating point hardware: micro-parallelism, micro-cycles
Message-ID: <41534@mips.mips.COM>
Date: 17 Sep 90 16:55:56 GMT
References: <197@validgh.com> <CHUCK.PHILLIPS.90Sep9215755@halley.FtCollins.NCR.COM> <41518@mips.mips.COM> <CHUCK.PHILLIPS.90Sep17040818@halley.FtCollins.NCR.COM>
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Reply-To: mash@mips.COM (John Mashey)
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In article <CHUCK.PHILLIPS.90Sep17040818@halley.FtCollins.NCR.COM> Chuck.Phillips@FtCollins.NCR.COM (Chuck.Phillips) writes:
...
>John> However, the reduced number of instructions is the LEAST of the issues,
>John> and people keep getting confused with this.  Much more relevant are
....

>Well put.  So how about ditching the RISC acronym for a more descriptive
>one?  (e.g. LOUIS - Load/store One Uniform Instruction Size   1/2 :-)

1) Would be nice, but we're probably stuck with it ...

2) And besides, I'd have to rewrite all of my foils that explain why
RISC (in sense of Reduced) has confused everybody :-)  My usual sequence
of acronyms is:
	Reduced Instruction Set Computer- not really
	Reusable Information Storage Computer-better (Marty Hopkins of IBM)
	Revolutionary Innovation in Science of Computing-no; Seymour at it 25yrs
	Response to Inherent Shifts in Computer technology -yes
-- 
-john mashey	DISCLAIMER: <generic disclaimer, I speak for me only, etc>
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