Path: utzoo!attcan!uunet!cs.utexas.edu!swrinde!zaphod.mps.ohio-state.edu!mips!winchester!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: Interrupts in user space Message-ID: <41537@mips.mips.COM> Date: 17 Sep 90 17:08:14 GMT References: <12738@encore.Encore.COM> Sender: news@mips.COM Reply-To: mash@mips.COM (John Mashey) Organization: MIPS Computer Systems, Inc. Lines: 36 In article <12738@encore.Encore.COM> jkenton@pinocchio.encore.com (Jeff Kenton) writes: >With the recent RISC chips (88000, MIPS and i860 come to mind) the overhead >of getting the machine state safely saved away in the low level exception >code is substantial. You have to do this anyway before you can hand off >control to the user program "without going into the OS kernel", so the >savings don't amount to much. 1) In any machine, one must perform the appropriate state saving. 2) I recommend Mike O'Dell's paper in this summer's USENIX proceedings. He has some insightful comments about the injteraction of the interface to the kernel and aggressive hardware design. Specifically, he described the serious performance issues of overcommitting to the user (either explicitly, or even worse, implicitly) the state of the machine, and what can/cannot be expected in a signal-handling routine. As an early example, consider the pain caused many people by the implicit requirements inherent in the Bourne shell's use of memory-fault handling..... 3) This is not to say that minimal-overhead fault-handling is a bad thing - it isn't, just that it is another area where: a) One must be careful. b) Completely unexepected side-effects can pop up and bite you - in the case Mike described, providing the exepcted signal-handling behavior sometimes cost them 2X or more in performance. c) In general, exception-handling is one of the most difficult to get right, and stays the buggiest longest, and adds years to systems programmers' ages.... -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086