Path: utzoo!attcan!uunet!cs.utexas.edu!sdd.hp.com!zaphod.mps.ohio-state.edu!mips!winchester!mash From: mash@mips.COM (John Mashey) Newsgroups: comp.arch Subject: Re: Why floating point hardware: micro-parallelism, micro-cycles Summary: another acronym gone Message-ID: <41538@mips.mips.COM> Date: 17 Sep 90 17:19:15 GMT References: <197@validgh.com> <919@shakti.ncst.ernet.in> Sender: news@mips.COM Lines: 23 In article <919@shakti.ncst.ernet.in>, shri@ncst.ernet.in (H.Shrikumar) writes: > If only we defined RISC = REGULAR Instruction Set Computers ..... > ^^^^^^^ No, that doesn't work either. Many CISCs are as regular as RISCs, and some are more so. For instance, the VAX is pretty regular, as is the NSC 32K. Sometimes CISCs have completely regular addressing modes that RISCs don't (i.e., where you include base+index addressing, or auto-increment only one side of the load/store pairing). In any case, part of the point of the last posting was that the acronym didn't really matter much; of course, it's hardly the case that one can draw a precise line between RISCs and CISCs anyway, and in fact, being frenzied about which label to apply ismarketing, anyway. Much more relevant is to study the underlying issues about kinds of features that yield performance or not. You will note that Hennessy & Patterson's book doesn't waste a lot of time messing with RISC acronyms... -- -john mashey DISCLAIMER: UUCP: mash@mips.com OR {ames,decwrl,prls,pyramid}!mips!mash DDD: 408-524-7015, 524-8253 or (main number) 408-720-1700 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086