Path: utzoo!attcan!utgpu!cunews!bnrgate!bigsur!bnr-rsc!bcarh185!schow
From: schow@bcarh185.bnr.ca (Stanley T.H. Chow)
Newsgroups: comp.arch
Subject: Re: RISC vs. CISC? No, OS bug executing data...
Message-ID: <3334@bnr-rsc.UUCP>
Date: 17 Sep 90 02:51:10 GMT
References: <AGLEW.90Sep12014046@dwarfs.crhc.uiuc.edu> <26507@mimsy.umd.edu>
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Reply-To: bcarh185!schow@bnr-rsc.UUCP (Stanley T.H. Chow)
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In article <26507@mimsy.umd.edu> chris@mimsy.umd.edu (Chris Torek) writes:
>
>Note that, on all the machines that crashed *except one*, it was a bug
>in the OS and not in the chip.  The one exception?  A CISC.
>-- 
>In-Real-Life: Chris Torek, Univ of MD Comp Sci Dept (+1 301 405 2750)
>Domain:	chris@cs.umd.edu	Path:	uunet!mimsy!chris

kinda expected. Don't you think? After all, the whole point of RISC is
to move the complexity from the chip to the S/W. But it is still a nice
demonstration that the complexity didn't go away, just moved.   

Stanley Chow        BitNet:  schow@BNR.CA
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Me? Represent other people? Don't make them laugh so hard.