Path: utzoo!attcan!uunet!decwrl!wuarchive!cs.utexas.edu!asuvax!ncar!husc6!encore!pinocchio.encore.com
From: jkenton@pinocchio.encore.com (Jeff Kenton)
Newsgroups: comp.arch
Subject: Re: MISC
Message-ID: <12752@encore.Encore.COM>
Date: 19 Sep 90 12:32:30 GMT
References: <1990Sep18.162246.19572@eagle.lerc.nasa.gov>
Sender: news@Encore.COM
Distribution: comp.arch
Lines: 32

From article <1990Sep18.162246.19572@eagle.lerc.nasa.gov>, by xxremak@csduts1.lerc.nasa.gov (David A. Remaklus):
> 
> Most of what I have heard on the MISC chip is covered by confidential
> disclosure agreements.

There was an article in one of the trade magazines about this machine.  The
features I remember are:

	.  128 bit instructions -- 64 bits to control the functional units
		and 2 32-bit addresses.

	.  No registers.  Everything is memory to memory.

	.  Only 9 basic (presumably low level) instructions.  The "opcode"
		bits directly control the hardware with no decoding.

	.  I have no idea what the functional units are, nor the instruction
		set.

	.  Typical memory requirements are exxpected to be higher than with
		current processors.  "Less than 10 times as much."

	.  Projected ship date is 1991 (1992?).

Sounded to me like an interesting approach but without enough details
to be sure.  Additions and corrections invited.


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