Path: utzoo!attcan!uunet!tut.cis.ohio-state.edu!pt.cs.cmu.edu!sei!firth
From: firth@sei.cmu.edu (Robert Firth)
Newsgroups: comp.arch
Subject: Re: MISC
Message-ID: <8663@fy.sei.cmu.edu>
Date: 19 Sep 90 16:26:20 GMT
References: <1990Sep14.173018.10197@batcomputer.tn.cornell.edu> <1990Sep14.205913.2146@cs.rochester.edu> <7707@ucdavis.ucdavis.edu> <2683@crdos1.crd.ge.COM>
Reply-To: firth@sei.cmu.edu (Robert Firth)
Distribution: comp.arch
Organization: Software Engineering Institute, Pittsburgh, PA
Lines: 11

In article <2683@crdos1.crd.ge.COM> davidsen@crdos1.crd.ge.com (bill davidsen) writes:

>  The minimal instruction set is probably 1 bit opcode field. One
>instruction is "add immediate and conditional branch" and the other is a
>NOP to put in the delay slot.

Aha! cried the dwarf, leaping on his shoulders... in that case, we can
construct a CISC version with a pipeline stall, so eliminating the need
for a NOP.  We now have a one-instruction machine with an encoding of
zero bits.  Of course, a typical program might need rather a lot of
them, but think how little memory they'll occupy!