Path: utzoo!attcan!uunet!samsung!uakari.primate.wisc.edu!sdd.hp.com!hplabs!hpl-opus!hpnmdla!hpsad!sdw From: sdw@hpsad.HP.COM (Steve Warwick) Newsgroups: comp.dsp Subject: DSP56001 cheat sheet Message-ID: <9520013@hpsad.HP.COM> Date: 18 Sep 90 22:26:51 GMT Organization: HP Signal Analysis Division - Rohnert Park, CA Lines: 372 the following is a convienent cheet sheet we have had lying around for the DSP56001. It still could use info on the assembler but it has been useful. enjoy. cut after stars, then use latex to format ****************************************** \documentstyle{article} %\setlength{\evensidemargin}{-0.5in} %\setlength{\oddsidemargin}{-0.5in} \setlength{\topmargin}{0in} \setlength{\headsep}{.1in} \begin{document} \title{\bf Motorola DSP56000 Instruction Set} \author{} \date{} \maketitle \begin{tabular}{rll} \multicolumn{3}{c}{\large \bf Condition Codes } \\ \\ Reference & Description & Formula \\ CC(HS) & Carry Clear & $C=0$\\ CS(LO) & Carry Set& $C=1$ \\ EC & Extension Clear & $E=0$ \\ EQ & Equal & $Z=1$ \\ ES & Extension Set & $E=1$ \\ GE & Greater Than or Equal & $N \oplus V=0$ \\ GT & Greater Than & $Z+(N \oplus V)=0$ \\ LC & Limit Clear & $L=0$ \\ LE & Less Than or Equal& $Z+(N \oplus V)=1$ \\ LS & Limit Set & $L=1$ \\ LT & Less Than & $N \oplus V=1$ \\ MI & Minus & $N=1$ \\ NE & Not Equal & $Z=0$ \\ NN & Not Normalized & $Z+(\bar{U} \cdot \bar{E})=0$ \\ NR & Normalized & $Z+(\bar{U} \cdot \bar{E})=1$ \\ PL & Plus & $N=0$ \\ \end{tabular} \medskip \medskip \begin{tabular}{rl} \multicolumn{2}{c}{\large \bf Data Move Conventions } \\ \\ $56 \rightarrow 24 $ & Takes middle word with limiting and scaling \\ $56 \rightarrow 48 $ & Takes both words with limiting and scaling \\ \medskip $24 \rightarrow 56 $ & Put in middle word with sign extention, low word zeroed\\ $24 \rightarrow 16 $ & Takes Low Order bits, discard rest \\ \medskip $16 \rightarrow 24 $ & Put in Low Order bits, Zero rest \\ $8 \rightarrow 16 $ & Put in Low Order bits, Zero rest \\ $8 \rightarrow 24 $ & \begin{minipage}[t]{4in} For A0,A1,A2,B0,B1,B2: Put in Low Order bits, Zero rest \\ For X0,X1,Y0,Y1,A,B: Put in High Order Bits, Zero rest \end{minipage} \end{tabular} \newpage \begin{tabular}{ll} \multicolumn{2}{c}{ \large \bf Address Modes by Type} \\ \\ \multicolumn{2}{l}{\bf Explicit Address Types} \\ \\ Absolute Address (16 Bits) & $\#xxxx$ \\ Short Data or Jump Address (12 Bits) & $\#xxx$ \\ Absolute Short Address (6 Bits, Zero Extended) & $$ \\ I/O Short Address (6 Bits, Ones Extended) & $$ \\ \\ \multicolumn{2}{l}{\bf $$ - Effective Address Types} \\ \\ No Update & $(R_{n})$ \\ Postincrement/Postdecrement by 1 & $(R_{n})\pm$ \\ Postincrement/Postdecrement by $N_{n}$ & $(R_{n})\pm N_{n}$ \\ Predecrement by 1 & $-(R_{n})$ \\ Indexed by $N_{n}$ & $(R_{n}+N_{n})$ \\ Absolute Address & xxxx \\ \\ \multicolumn{2}{l}{\bf $|$ - X,Y Effective Address Types} \\ \\ No Update & $(R_{n})$ \\ Postincrement/Postdecrement by 1 & $(R_{n})\pm$ \\ Postincrement/Postdecrement by $N_{n}$ & $(R_{n})\pm N_{n}$ \\ \\ \multicolumn{2}{l}{U - \bf Register Update Mode} \\ \\ Postincrement/Postdecrement by 1 & $(R_{n})\pm$ \\ Postincrement/Postdecrement by $N_{n}$ & $(R_{n})\pm N_{n}$ \\ \\ \multicolumn{2}{l}{ S,D - \bf Source or Destination Registers: } \\ \multicolumn{1}{r}{(24 Bits)}& X0,X1,Y0,Y1 \\ & A0,A1,A2,B0,B1,B2 \\ \multicolumn{1}{r}{(16 Bits)}& R0-R7,N0-N7 \\ \multicolumn{1}{r}{(56 Bits)}& A,B (With Numeric Rounding) \\ \\ \multicolumn{2}{l} { SL,DL - \bf Long Word Registers: } \\ \multicolumn{1}{r}{(48 Bits)}& X,Y \\ & AB,BA (Same as A1,B1) \\ & A10,B10 \\ & A,B (With Numeric Rounding) \\ \\ \multicolumn{2}{l}{Cn - \bf Control Registers: } \\ & SR OMR SP SSH SSL LA LC M0-M7 \end{tabular} \newpage \centering{\large \bf Instruction Syntax} \vspace{.25in} \small \begin{tabular}{llclp{2.0in}} Mneumonic & Description & Parallel & Syntax \\ & & Move & \\ \hline \\ ABS & Absolute Value & $\bullet$ & ABS $[A|B]$ \\ \\ ADC & Add Long w/Carry & $\bullet$ & ADC $[X|Y]$,$[A|B]$ \\ \\ ADD & Add & $\bullet$ & ADD $[X|Y|X0|X1|Y0|Y1]$,$[A|B]$\\ & & $\bullet$ & ADD $A,B$\\ & & $\bullet$ & ADD $B,A$\\ ADDL & Shift Left \& Add & $\bullet$ & ADDL $A,B$ \\ & & $\bullet$ & ADDL $B,A$ \\ ADDR & Shift Right \& Add & $\bullet$ & ADDR $A,B$ \\ & & $\bullet$ & ADDR $B,A$ \\ AND & Logical AND (24 bit only) & $\bullet$ & AND $[X0|X1|Y0|Y1]$,$[A,B]$ \\ \\ ANDI & AND Immed Cntl Reg & & AND(I) \#xx,$[\rm{MR}|\rm{CCR}|\rm{OMR}]$ \\ \\ ASL & Arithmetic Shift Left (56 Bits)& $\bullet$ & ASL $[A|B]$ \\ \\ ASR & Arithmetic Shift Right (56 Bits)& $\bullet$ & ASR $[A|B]$ \\ \\ BCHG & Bit Test \& Change & & BCHG \#n,$[X|Y]$:$[||]$ \\ & & & BCHG \#n,$[D|Cn]$ \\ BCLR & Bit Test \& Clear & & BCLR \#n,$[X|Y]$:$[||]$ \\ & & & BCLR \#n,$[D|Cn]$ \\ BSET & Bit Test \& Set & & BSET \#n,$[X|Y]$:$[||]$ \\ & & & BSET \#n,$[D|Cn]$ \\ BTST & Bit Test on Memory & & BTST \#n,$[X|Y]$:$[||]$ \\ & & & BTST \#n,$[D|Cn]$ \\ CLR & Clear Accum & $\bullet$ & CLR $[A|B]$ \\ \\ CMP & Compare (D-S)& $\bullet$ & CMP $[X0|X1|Y0|Y1]$,$[A|B]$ \\ & & $\bullet$ & CMP $A,B$ \\ & & $\bullet$ & CMP $B,A$ \\ \\ CMPM & Compare Magnitude ($|D|-|S|$) & $\bullet$ & CMPM $[X0|X1|Y0|Y1]$,$[A|B]$ \\ & & $\bullet$ & CMPM $A,B$ \\ & & $\bullet$ & CMPM $B,A$ \\ DIV & Divide Iteration & & DIV $[X0|X1|Y0|Y1]$,$[A|B]$ \end{tabular} \begin{tabular}{llclp{2.0in}} Mneumonic & Description & Parallel & Syntax \\ & & Move & \\ \hline \\ DO & Start Hardware Loop & & DO $[X|Y]$:$[|]$,xxxx \\ & & & DO \#xxx,xxxx & \\ & & & DO $[S|Cn]$,xxxx & \\ ENDDO & End Current DO Loop & & ENDDO & \\ \\ EOR & Logical Exclusive OR & $\bullet$ & EOR $[X0|X1|Y0|Y1]$,$[A|B]$\\ \\ ILLEGAL & Illegal Instr Interrupt & & ILLEGAL & \\ \\ Jcc & Jump Conditionally & & Jcc $[xxx|]$\\ \\ JCLR & Jump if Bit Clear & & JCLR \#n,$[X|Y]$:$[||]$,xxxx & \\ & & & JCLR \#n,$[S|Cn]$,xxxx \\ JMP & Jump & & JMP $[xxx|]$ \\ \\ JScc & JSR Conditionally & & JScc $[xxx|]$ & \\ JSCLR & JSR if Bit Clear & & JSCLR \#n,$[X|Y]$:$[||]$,xxxx & \\ & & & JSCLR \#n,$[S|Cn]$,xxxx \\ JSET & Jump if Bit Set & & JSET \#n,$[X|Y]$:$[||]$,xxxx & \\ & & & JSET \#n,$[S|Cn]$,xxxx \\ JSR & Jump to Subroutine & & JSR $[xxx|]$ \\ \\ JSSET & JSR if Bit Set & & JSSET \#n,$[X|Y]$:$[||]$,xxxx & \\ & & & JSSET \#n,$[S|Cn]$,xxxx \\ LSL & Logical Shift Left (24 bit only)& $\bullet$ & LSL $[A|B]$ \\ \\ LSR & Logical Shift Right (24 bit only)& $\bullet$ & LSR $[A|B]$ \\ \\ LUA & Load Updated Addr & & LUA $[]$,$[Rn|Nn]$ \\ \\ MAC & Multiply-Accumulate & $\bullet$ & MAC $ (\pm) [X0|X1|Y0|Y1], [X0|X1|Y0|Y1],[A|B]$ \\ & & & Except: $X1,X1,[A|B]$ and $Y1,Y1,[A|B]$ \\ MACR & MAC \& Round & $\bullet$ & MACR $ (\pm) [X0|X1|Y0|Y1], [X0|X1|Y0|Y1],[A|B]$ \\ & & & Except: $X1,X1,[A|B]$ and $Y1,Y1,[A|B]$ \\ MOVEC & Move Cntl Reg & & MOVEC $[X|Y]:[|]$,$[Cn]$ \\ & & & MOVEC $[Cn]$,$[X|Y]:[|]$ \\ & & & MOVEC $[S|Cn]$,$[Cn]$ \\ & & & MOVEC $[Cn]$,$[D|Cn]$ \\ & & & MOVEC \#xxxx,$[Cn]$ \\ \medskip & & & MOVEC \#xx,$[Cn]$ \\ & & & \parbox[t]{2.5in} {Note - moves into/out of SSH increment/decrement Stack Pointer SP} \\ \end{tabular} \begin{tabular}{llclp{2.0in}} Mneumonic & Description & Parallel & Syntax \\ & & Move & \\ \hline \\ MOVEM & Move Pgm Memory & & MOVEM $[S|Cn]$S,P:$[|]$ \\ & & & MOVEM P:$[|]$,$[D|Cn]$ \\ MOVEP & Move Peripheral & & MOVEP $[X|Y]:$,$[X|Y]:$ \\ & & & MOVEP $[X|Y]:$,$[X|Y]:$\\ & & & MOVEP \#xxxxxx,$[X|Y]:$\\ & & & MOVEP $[X|Y]:$,$[D|Cn]$\\ & & & MOVEP $[S|Cn]$,$[X|Y]:$\\ MPY & Multiply & $\bullet$ & MPY $ (\pm) [X0|X1|Y0|Y1], [X0|X1|Y0|Y1],[A|B]$ \\ & & & Except: $X1,X1,[A|B]$ and $Y1,Y1,[A|B]$ \\ MPYR & Multiply \& Round & $\bullet$ & MPYR $ (\pm) [X0|X1|Y0|Y1], [X0|X1|Y0|Y1],[A|B]$ \\ & & & Except: $X1,X1,[A|B]$ and $Y1,Y1,[A|B]$ \\ NEG & Negate Accum & $\bullet$ & NEG $[A|B]$ \\ \\ NOP & No Operation & & NOP & \\ \\ NORM & Normalize Iteration & & NORM Rn,$[A|B]$\\ \\ NOT & Logical Complement (24 bit only)& $\bullet$ & NOT $[A|B]$ \\ \\ OR & Inclusive OR (24 bit only)& $\bullet$ & OR $[X0|X1|Y0|Y1]$,$[A,B]$ \\ \\ ORI & OR Immed Cntl Reg & & OR(I) \#xx,$[\rm{MR}|\rm{CCR}|\rm{OMR}]$ \\ \\ REP & Repeat Next Instruction & & REP $[X|Y]:[|]$ & \\ & & & REP $[S|Cn|\#xxx]$ \\ RESET & Reset Peripheral Devices & & RESET & \\ \\ RND & Round Accum & $\bullet$ & RND $[A|B]$ \\ \\ ROL & Rotate Left (24 bit only) & $\bullet$ & ROL $[A|B]$ \\ \\ ROR & Rotate Right (24 bit only) & $\bullet$ & ROR $[A|B]$ \\ \\ RTI & Return from Interrupt & & RTI & \\ \\ RTS & Return from Subroutine & & RTS & \\ \\ SBC & Subtract Long w/Carry & $\bullet$ & SBC $[X|Y]$,$[A|B]$ \\ \\ STOP & Stop Processor & & STOP & \\ \end{tabular} \begin{tabular}{llclp{2.0in}} Mneumonic & Description & Parallel & Syntax \\ & & Move & \\ \hline \\ SUB & Subtract & $\bullet$ & SUB $[X|Y|X0|X1|Y0|Y1]$,$[A|B]$\\ & & $\bullet$ & SUB $A,B$\\ & & $\bullet$ & SUB $B,A$\\ SUBL & Shift Left \& Subtract & $\bullet$ & SUBL A,B & \\ & & $\bullet$ & SUBL B,A & \\ SUBR & Shift Right \& Subtract & $\bullet$ & SUBR A,B & \\ & & $\bullet$ & SUBR B,A & \\ SWI & Software Interrupt & & SWI & \\ \\ Tcc & Transfer Conditionally & & TCC $[X0|X1|Y0|Y1]$,$[A|B]$ Rn,Rn \\ & & & TCC A,B Rn,Rn \\ & & & TCC B,A Rn,Rn \\ & & & (Rn,Rn Optional) \\ TFR & Transfer Data ALU Reg & $\bullet$ & TFR $[X0|X1|Y0|Y1]$,$[A|B]$ \\ & & $\bullet$ & TFR A,B \\ & & $\bullet$ & TFR B,A \\ TST & Test Accum & $\bullet$ & TST $[A|B]$ \\ \\ WAIT & Wait for Interrupt & & WAIT & \\ \end{tabular} \newpage \centering{\large \bf Parallel Move Instruction Syntax} \vspace{.25in} \begin{tabular}{rll} {\bf Single Moves:} &\\ \\ Move Immediate & \#xx,D \\ & \#xxxx,D \\ Register To Register & S,D \\ Update Only & U \\ Memory Source or Dest & $[X|Y]:[|],D$ \\ & $S,[X|Y]:[|]$ \\ \\ Long Memory: \\ \\ & L:$[|]$,DL \\ & SL,L:$[|]$ \\ {\bf Combined Moves:} & \\ \\ One Memory, One Register\\ \\ & $X:,[X0|X1|A|B]$ & $[A|B],[Y0|Y1]$ \\ & $[X0|X1|A|B],X:$ & $[A|B],[Y0|Y1]$ \\ \\ & $Y:,[Y0|Y1|A|B]$ & $[A|B],[X0|X1]$ \\ & $[Y0|Y1|A|B],Y:$ & $[A|B],[X0|X1]$ \\ \\ & $A,X:$ & $X0,A$ \\ & $B,X:$ & $X0,B$ \\ \\ & $A,Y:$ & $Y0,A$ \\ & $B,Y:$ & $Y0,B$ \\ \\ & $\#xxxx,[X0|X1]$ & $[A|B],[Y0|Y1]$ \\ & $\#xxxx,[Y0|Y1]$ & $[A|B],[X0|X1]$ \\ \\ & $\#xxxx,[A|B]$ & $[A|B],[X0|X1|Y0|Y1]$ \\ \\ Two Memory Moves \\ \\ & $ \left\{ \begin{array}{c} X:,\rm{[}X0|X1|A|B\rm{]} \\ \rm{[}X0|X1|A|B\rm{]} , X: \end{array} \right\} $ & $ \left\{ \begin{array}{c} Y:,\rm{[}Y0|Y1|A|B\rm{]} \\ \rm{[}Y0|Y1|A|B\rm{]} , Y: \end{array} \right\} $ \\ \\ \multicolumn{3}{c} {Note - Register specified in $$ cannot be in the same set (R0-R3,R4-R7) as $$} \end{tabular} \end{document}