Path: utzoo!attcan!uunet!optilink!manley
From: manley@optilink.UUCP (Dave Manley)
Newsgroups: comp.lsi.cad
Subject: VLSI Technology place and route tools for gate arrays
Message-ID: <4470@optilink.UUCP>
Date: 17 Sep 90 23:00:16 GMT
Organization: Optilink Corporation, Petaluma, CA
Lines: 32

Has anyone out there had personal experience with these tools and
could they comment on the following points:

Do (can) the placement tools use the hierarchical netlist to obtain a
better placement than is available from the flattened netlist?  I
assume the extra information in the hierarchical netlist could be
used to do this?

How are the net 'weights' used by the router?  Do the nets with
higher weights get routed first?  The weights are not in the flattened
netlist - why?

What routing strategies does the router use?

What experience have you had with the larger gate arrays (>40 
raw gates) with regards to utilization.

What problems, if any have you had with clock skew in the clock
distribution tree?

Any information on any of these subjects would be welcomed.

Thanks in advance,

**************************************************
*	Dave Manley
*	Optilink Corporation
*	Petaluma, CA
*	707-795-9444
*
*	{uunet|pyramid}!optilink!manley
**************************************************