Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!uunet!optilink!manley
From: manley@optilink.UUCP (Dave Manley)
Newsgroups: comp.lsi.cad
Subject: Re: VLSI Technology place and route tools for gate arrays
Summary: oops...
Message-ID: <4476@optilink.UUCP>
Date: 18 Sep 90 04:41:00 GMT
References: <4470@optilink.UUCP>
Organization: Optilink Corporation, Petaluma, CA
Lines: 21

In article <4470@optilink.UUCP>, manley@optilink.UUCP (Dave Manley) writes:

> What experience have you had with the larger gate arrays (>40 gates)
> with regards to utilization.
> 
One of my fellow workers suggests that 40 gates isn't all that much.
So let me try again...

Our actual gate counts are in the 15k-25k gate range which puts us 
into 46k to 77k gate devices.  

 Thanks again, 
 
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 *	Dave Manley
 *	Optilink Corporation
 *	Petaluma, CA
 *	707-795-9444
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 *	{uunet|pyramid}!optilink!manley
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