Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!wuarchive!zaphod.mps.ohio-state.edu!van-bc!mdivax1!moss
Newsgroups: comp.lsi.cad
Subject: Re: VLSI Technology place and route tools for gate arrays
Message-ID: <1990Sep18.162644.3311@mdivax1.uucp>
Date: 18 Sep 90 16:26:44 GMT
References: <4470@optilink.UUCP>
Reply-To: mdivax1!moss (Barry Moss)
Organization: Mobile Data International, Richmond, B.C., Canada
Lines: 23
Return-Path: <mdivax1!news>
Apparently-To: van-bc!rnews

In article <4470@optilink.UUCP> manley@optilink.UUCP (Dave Manley) writes:
>Has anyone out there had personal experience with these tools and
>could they comment on the following points:
>
>Do (can) the placement tools use the hierarchical netlist to obtain a
>better placement than is available from the flattened netlist?  I
>assume the extra information in the hierarchical netlist could be
>used to do this?
>
I have recently completed a 2.3K gate array design with Oki logic 
using Valid Logic's GED schematic capture.  Valid "flattens" the
design as part of the compilation of the netlist.  Looking at some
of the reports that Oki produces, it would appear that their system
performs a net list translation without regard to the hierarchical
netlist names; therefore, I would assume that their router does not
use heirarchical information to produce a better placement.

Just one person's experience.

Barry Moss
Design Engineer
Mobile Data International
(A Motorola Company)