Path: utzoo!attcan!uunet!bywater!arnor!ibm.com!dgreen
From: dgreen@ibm.com (Dan R. Greening)
Newsgroups: comp.lsi.cad
Subject: Re: VLSI Technology place and route tools for gate arrays
Message-ID: <1990Sep18.151012.1177@arnor.uucp>
Date: 18 Sep 90 15:10:12 GMT
References: <4470@optilink.UUCP>
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Reply-To: dgreen@cs.ucla.edu
Organization: UCLA & IBM T.J.Watson Research Center
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manley@optilink.UUCP (Dave Manley) writes:

|> Has anyone out there had personal experience with these tools and
|> could they comment on the following points:
|> 
|> Do (can) the placement tools use the hierarchical netlist to obtain a
|> better placement than is available from the flattened netlist?  I
|> assume the extra information in the hierarchical netlist could be
|> used to do this?

Some commercial tools do use the hierarchy to help place the circuits.
I believe that Seattle Silicon's product, for example, does this.

However, it isn't all that clear that using the hierarchy necessarily
helps.  In some cases, yes.  In others, no.

I believe this is an open research area.  The following reference may
provide some help, in itself, through its reference list, or through
references to it (see Scientific Citation Index in a good science 
library).

  J. Rose, W. Klebsch and J. Wolf, Temperature Measurements and
  Equilibrium Dynamics of Simulated Annealing Placements, IEEE 
  Transactions on CAD, v 9, n 3 (March 1990) p 253-259.

Dan Greening		12 Foster Court			NY (914) 784-7861
dgreen@cs.ucla.edu	Croton-on-Hudson, NY 10520	CA (213) 825-2266