Path: utzoo!utgpu!watserv1!watmath!att!occrsh!uokmax!apple!goofy.apple.com!esmith From: esmith@goofy.apple.com (Eric Smith) Newsgroups: sci.electronics Subject: Re: Digital Out (Philips CD620) Message-ID: Date: 12 Sep 90 01:11:29 GMT References: <704@hexagon.se> <1770016@otter.hpl.hp.com> Sender: usenet@Apple.COM Organization: Frobozz Magic Widget Company Lines: 82 In-reply-to: sgm@otter.hpl.hp.com's message of 11 Sep 90 10:15:29 GMT In article <1770016@otter.hpl.hp.com> sgm@otter.hpl.hp.com (Steve Methley) writes: > > I'm looking for the specifications of the DIGITAL OUT signal on > > the Philips CD620. I guess it's some kind of standard. > > I've mailed the original poster, but I think it's general interest; - you can > get details from Philips Data Book 4 Part IC01, under part number SAA7220. > Here you can find voltage levels and recommended load etc...... >n > It is a standard produced by Philips and Sony and used in very many CD players, > although sometimes the data is inverted before transmission for no apparent > reason. The reason the data is sometimes inverted is that the digital audio interconnect standard specifically states that the polarity of the signal is undefined, and is allowed to change (even on one piece of equipment). Since the code is self-clocking (Biphase Mark), the polarity doesn't matter at all. In biphase mark encoding, there is a transition on the line between each pair of bit cells. There is an additional transition in the center of the bit cell for 1 bits. This is equivalent to frequency modulation. To receive the code, you use a PLL to recover the clock, and you can easily do away with the polarity problem by differentiating the data, something like this ____ Input Signal >---+------------------+--------------\ \ \ | | | |XOR|----- Output | | ------ +--/ /___/ | +---|D Q|--+ | ------- | | +--| PLL |--clock--+---|> | ------- | ------ | +-------------------------- Clock where the PLL recovers the half-bit cell clock, and the output will be a one for one clock cycle whenever the input transitions. Then you need to detect the three different sync patterns. I use a PAL as a shift register and comparator to do this. Data Input (on wire or optical) Output of circuit above __ __ 1 / \__/ or \__/ \ 11 _____ 0 / \ or \_____/ 10 ________ __ Sync / \________/ \__/ 10010011 or ________ __ \________/ \__/ \ ________ ________ Sync / \__/ \__/ 10011001 or __ __ \________/ \________/ \ ________ __ Sync / \__/ \________/ 10011100 or __ ________ \________/ \__/ \ Note that the sync patterns take 4 bit times (8 half-bits), and do not meet the normal biphase mark encoding rules. I don't remember the designations or meanings of the sync patterns offhand. There is one for the left channel sub-frame, one for the right channel sub-frame, and one that is used every 192 frames to indicate the beginning of a channel status block. Of course, the simplest way to deal with it is to use a receiver chip, such as the Yamaha DIR or DIR-2. These have the PLL and decode the bit stream, to give you a serial digital audio stream without the extra junk, and a subset of the channel status info. -- Eric L. Smith Opinions expressed herein do not necessarily reflect those esmith@apple.com of my employer, friends, family, computer, or even me! :-)