Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!samsung!uunet!mcsun!hp4nl!svin02!rcpieter
From: rcpieter@svin02.info.win.tue.nl (Tiggr)
Newsgroups: comp.arch
Subject: Re: Acorn RISC Machine memory management
Keywords: ARM, Acorn, MMU, 4MB
Message-ID: <1436@svin02.info.win.tue.nl>
Date: 21 Sep 90 16:25:05 GMT
References: <13942@hydra.gatech.EDU>
Organization: Eindhoven University of Technology, The Netherlands
Lines: 18

ken@dali.gatech.edu (Ken Seefried iii) writes:

>Is Acorn and/or VLSI Technologies working on an updated MMU for the
>ARM?  Surely noone 'round there thinks 32MB processes and a 4MB
>physical memory is remotely adequate....

Ahem.  The numbers should read 32Mb logical address space (i.e. the kernel
must fit in there somewhere as well), and 16Mb physical memory space (by using
4 memory controllers (the maximum)).

The 32Mb _is_ imposed by MEMC1.  But remember that the ARM only has 26 address
lines, giving 64Mb addressable memory.  Hacking it to have it have more address
lines is non trivial, since the software model of the CPU would change, because
the 32 bit PC register also contains the status and mode flags...

But this doesn't answer your question...

Tiggr