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From: steves@sv001.SanDiego.NCR.COM (Steve Schlesinger x3711)
Newsgroups: comp.arch
Subject: Re: Is handling off-alignment important?
Message-ID: <674@iss-rb.SanDiego.NCR.COM>
Date: 10 Aug 90 19:09:45 GMT
References: <40711@mips.mips.COM>
Sender: news@iss-rb.SanDiego.NCR.COM
Reply-To: steve.schlesinger@SanDiego.NCR.COM (x3711)
Organization: JD-NCR/Teradata, San Diego CA
Lines: 28

From article <40711@mips.mips.COM>, by mash@mips.COM (John Mashey):
> 
> Just out of curiosity, can anyone give some live examples where software
> takes advantage of the mode where the CPU just zeroes the low-oorder
> bits and conitnues, as in the 88K?  (or, I think(?), in the RT/PC).
>

When emulating other (older) architectures that permit non-aligned accesses,
there are two basic choices with architectures of this type:

1	examine the nonaligned memory access and read ALIGNED bytes,
	ALIGNED halfwords and/or ALIGNED words as appropriate and
	shift and mask them together.

2	do two NON-ALIGNED reads of the two memory words the nonaligned word
	straddles ( non-aligned-addr and non-aligned-addr+4 ) and then
	shift and mask.

	The low order bits are ignored by the read, but are used by the
	masking and shifting code.

My memory of this is fuzzy, but in most cases, (2) is more efficient.


===============================================================================
Steve Schlesinger, NCR/Teradata Joint Development				   619-597-3711
11010 Torreyana Rd, San Diego, CA 92121		 steve.schlesinger@sandiego.ncr.com
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