Path: utzoo!utgpu!news-server.csri.toronto.edu!mailrus!uunet!samsung!zaphod.mps.ohio-state.edu!usc!apple!voder!dtg.nsc.com!my
From: my@dtg.nsc.com (Michael Yip)
Newsgroups: comp.arch
Subject: Re: Discontintuiy
Message-ID: <1425@berlioz.nsc.com>
Date: 24 Sep 90 05:48:51 GMT
References: <10550@pt.cs.cmu.edu>
Reply-To: my@berlioz.UUCP (Michael Yip)
Organization: National Semiconductor, Santa Clara
Lines: 13

Instead of just expanding the on-chip cache size there are many things
that we can do to use up that 49 million transisters (;-).

We can probably integrate some specialized functional units on-chip.
For example, units for vector processing and units for off loading
the routing of mesages (for Transputers).  Or even put many processors
on the same Si and have parallel processing on one chip.

I am not an expert to computer architecture but it is interesting to
see what we can do in a few years (hopefully).  

-- Mike
   my@dtg.nsc.com