Path: utzoo!utgpu!news-server.csri.toronto.edu!cs.utexas.edu!sun-barr!apple!rutgers!rochester!pt.cs.cmu.edu!o.gp.cs.cmu.edu!TR4.GP.CS.CMU.EDU!spot
From: spot@TR4.GP.CS.CMU.EDU (Scott Draves)
Newsgroups: comp.arch
Subject: Re: F.P. vs. arbitrary-precision
Message-ID: <1990Sep11.035826.22880@cs.cmu.edu>
Date: 11 Sep 90 03:58:26 GMT
References: <3755@osc.COM> <4513@taux01.nsc.com> <119244@linus.mitre.org> <3977@bingvaxu.cc.binghamton.edu> <2538@l.cc.purdue.edu>
Sender: netnews@cs.cmu.edu (USENET News Group Software)
Reply-To: spot@TR4.GP.CS.CMU.EDU (Scott Draves)
Organization: Carnegie Mellon University
Lines: 23

Herman Rubin sez:
>The design time to make a decent integer multiplier, if you are going to
>have a floating point multiplier, is essentially ZERO.  How do you think

This integer multiply would have to be a fp instruction, because the
chip probably has separate integer and fp register files, and/or it
is super-scalar.  11 bits plus extra control stuff doesn't sound like
ZERO work to me.

Anyway, exactly how much slower is it to hand-code arbitrary precision
arithmetic? 10 times?  100 times?  Do I really care? Do the chip makers
care? What fraction of people use fp compared with arb. prec. arith?
How often would your bit stream instruction(s) be used?  What are the
chances that it would fit into a RISC pipeline?

You're right when you complain that chips these days aren't good for
what you do.  But I don't care, and neither do many other people.
Flame off.


			Consume
Scott Draves		Be Silent
spot@cs.cmu.edu		Die