Path: utzoo!attcan!uunet!decwrl!fernwood!portal!cup.portal.com!mmm
From: mmm@cup.portal.com (Mark Robert Thorson)
Newsgroups: comp.arch
Subject: Cache Line Fills -- Critical Word First
Message-ID: <34275@cup.portal.com>
Date: 26 Sep 90 05:20:58 GMT
Organization: The Portal System (TM)
Lines: 28

When some caches miss, they just go out to memory and snort up a line in
sequential order.  I believe the MIPS R6000 is an example of this.

But with most designs, such as the 486, SPARC, 68040, etc., the first
item to be returned to the CPU is the item which caused the miss.  This
is called "critical word first".

One difference between the 486 and everybody else is that the 486 will
always read the next word from the other half of an aligned 2-word block
before reading the other two words needed to fill a cache line.

For example, if the miss is on address xxx1, the 486 will fill the cache line
in the order 1-0-3-2.  On SPARC or the 68040, the read continues to the end
of the block and wrapsaround, i.e. 1-2-3-0.

Why did Intel do it this way?  To optimize the performance of 64-bit
memory systems.  Using the conventional order, the CPU might read one word
from one 64-bit block, read two words from a second block, then hop back to the
first block for another word.  Intel's method always reads one block before
reading the other.

Does this little design tweak pay off?  Just recently, Motorola has provided
proof!  They've introduced two static RAM's with on-chip burst control logic
optimized for use as cache memories.  The MCM62940 is compatible with
conventional burst ordering.  The MCM62486 uses Intel-style burst ordering.
The MCM62940 is offered in the following speed grades: 15, 20, and 25 ns.
(Max. access time.)  The MCM62486 is offered in:  14, 19, and 24 ns.  Intel
wins by a nanosecond!